The present invention relates to a method and system for evaluating the shape of a circuit pattern, which is formed on a wafer during a semiconductor manufacturing process, by using an electron microscope image of the circuit pattern, which is obtained by an electron microscope, and more particularly to a method for measuring a measurement target pattern with an electron microscope.
In a semiconductor wafer manufacturing process, a multilayer pattern formed on a wafer has been rapidly rendered microscopic. Therefore, process monitoring for checking whether the pattern is formed on the wafer in compliance with design specifications has become increasingly important. The wiring widths of transistor gate wiring patterns and other similar wiring patterns are significantly associated with device performance. Therefore, it is particularly important that a wiring manufacturing process for such wiring patterns be properly monitored.
A critical dimension scanning electron microscope (CD-SEM), which is capable of picking up a wiring image at magnifications of 100000× to 200000×, has been conventionally used as a tool for measuring the wiring width of a microscopic wiring on the order of several tens of nanometers.
An example of a length measurement process performed with a scanning electron microscope is described in Japanese Patent JP-A No. 316115/1999. The process disclosed by Japanese Patent JP-A No. 316115/1999 examines a local region within an image of a measurement target wiring, creates a projection profile by averaging a wiring signal profile in a longitudinal direction of wiring, and calculates a wiring dimension as the distance between right- and left-hand wiring edges detected in the created profile.
However, as disclosed by J. S. Villarrubia, A. E. Vladar, J. R. Lowney, and M. T. Postek, “Scanning electron microscope analog of scatterometry,” Proc. SPIE 4689, pp. 304-312 (2002) (hereinafter referred to Proc. SPIE 4689), the SEM signal waveform changes in accordance with a change in the shape of a target pattern to be measured. This causes a measurement error. As semiconductor patterns are becoming increasingly microscopic, the influence of such a measurement error on process monitoring is becoming greater. A method for reducing such a measurement error is disclosed by J. S. Villarrubia, A. E. Vladar, and M. T. Postek, “A simulation study of repeatability and bias in the CD-SEM,” Proc. SPIE 5038, pp. 138-149, 2003 (hereinafter referred to as Proc. SPIE 5038). This method performs a simulation in advance to calculate the relationship between a pattern shape and SEM signal waveform and uses the obtained calculation results to make high-precision measurements that are not dependent on a target shape.